A computer aided design (“CAD”) tool is used to generate layouts for integrated circuitry. The CAD tool builds an integrated circuit design by utilizing pre-defined groups of electronic gates (known as “cells”) stored in a cell library. Each of the electronic gates is formed by one or more field effect transistors (FETs) characterized in polarity as either p-type or n-type. A cell tool is used by a designer to create and edit the cells. A SPICE tool is then used to simulate the operational behavior of each cell to determine maximum and minimum signal propagation timing therein. The SPICE tool utilizes schematic component and connectivity information from the cell library, gate performance information from a gate library (typically supplied by a manufacturer), and a list of test vectors specifying input stimulation for each cell. These test vectors are written by a designer to ensure stimulation of the circuit paths associated with the maximum and minimum signal propagation timing. The signal propagation timing for each cell is then stored in a characterization library. Thereafter, the CAD tool uses cell schematic information from the cell library and cell characterization information from the characterization library to specify the integrated circuit design.
The writing of test vectors and the use of the test vectors with the SPICE tool during cell simulation is labor-intensive and time-consuming. Any changes to gate definitions in the gate library, or to cells in the cell library, require that (a) the test vectors be updated and (b) the SPICE tool re-simulate the cells to update the characterization information in the characterization database.